QL6500-7PB516I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6500-7PB516I' PDF : 73 Pages View PDF
Eclipse Family Data Sheet Rev. F
Clock Networks
Global Clocks
There are eight global clock networks in the Eclipse device family. Global clocks can drive logic cell, I/O, and
RAM blocks in the device. Five global clocks have access to a Quad Net (local clock network) connection with
a programmable connection to the register inputs. Global clock pins are 2.5 V, LVCMOS2, compliant.
Figure 9: Global Clock Methodology
Quad Net
Global Clock Net
CLK Pin
12
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