QL7100-6PB516I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7100-6PB516I' PDF : 65 Pages View PDF
EclipsePlus Family Data Sheet Rev. A
Figure 8: Logic Cell Flip-Flop Timings—Second Waveform
CLK
D
tSU
tHL
Q
tCO
Figure 9: EclipsePlus Global Clock Structure
Quad net
Clock Segment
tPGCK
tBGCK
Table 7: Eclipse Global Clock Tree Delays
Parameter
Global clock pin delay to quad net
Value (ns)
Max. Rise
Max. Fall
0.990
1.386
Global clock buffer delay (quad net to flip flop)
0.534
1.865
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