QL7100-7PT208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7100-7PT208C' PDF : 42 Pages View PDF
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Instead of requiring extra components, designers simply need to instantiate one of the pre-
configured models described in this section and listed in 7DEOH . The QuickLogic built-in
PLLs support a wider range of frequencies than many other PLLs. Also, QuickLogic PLLs
can be cascaded to support different ranges of frequency multiplications or divisions, driving
the device at a faster or slower rate than the incoming clock frequency. Most importantly,
they achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out
time is achieved by the PLL subtracting the clock tree delay through the feedback path,
effectively making the clock tree delay zero.
)LJXUH illustrates a typical QuickLogic ESP PLL.
FIN
Frequency Divide
PLL Bypass
_..1
_.. 2
+
_.. 4
-
Filter
vco
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
FOUT
Frequency Multiply
_..1
_..2
_..4
)LJXUH 3// %ORFN
Fin represents a very stable high-frequency input clock and produces an accurate signal
reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly,
or it can pass through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin
signal and the local VCO form a control loop. The VCO is multiplied or divided down to the
reference frequency, so that a phase detector (the crossed circle in )LJXUH ) can compare
the two signals. If the phases of the external and local signals are not within the tolerance
required, the phase detector sends a signal through the charge pump and loop filter
()LJXUH ). The charge pump generates an error voltage to bring the VCO back into
alignment and the loop filter removes any high frequency noise before the error voltage
enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry.
Fout represents the clock signal that emerges from the output pad (the output signal
PLLPAD_OUT is explained in 7DEOH ). This clock signal is meaningful only when the PLL
is configured for external use; otherwise, it remains in high Z state, as shown in the post-
simulation waveform.
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