QL7100-7PT208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7100-7PT208C' PDF : 42 Pages View PDF
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The basic power equation which best models power consumption is given below:
PTOTAL = 0.350 + f[0.0031 ηLC + 0.0948 ηCKBF + 0.01 ηCLBF+ 0.0263 ηCKLD+
0.543 ηRAM + 0.20 ηPLL+ 0.0035 ηINP + 0.0257 ηOUTP] (mW)
Where
ηLC is the total number of logic cells in the design
ηCKBF = # of clock buffers
ηCLBF = # of column clock buffers
ηCKLD = # of loads connected to the column clock buffers
ηRAM = # of RAM blocks
ηPLL = # of PLLs
ηINP is the number of input pins
ηOUTP is the number of output pins
)LJXUH exhibits the power consumption in an EclipsePlus QL7100 device. The chip was
filled with (300) 8-bit countersapproximately 76% logic cell utilization.
Power vs Freq. (Counter_300)
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
140
Frequency (Mhz)
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)LJXUH illustrates the theoretical worst-case scenarios for 50%, 70%, and 90% utilizations
of the 6600-516 package. The resources of the device are divided exactly in half; meaning,
for 50% utilization, exactly 50% of the I/Os, Logic Cells, RAM blocks, clock network, etc.
are utilized. These situations may never occur in a real design, but they do provide a very
rough quantitative measure of power consumption when talking in terms of 50% or 70%
utilization of an EclipsePlus device.
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