QL7120-5PS484M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7120-5PS484M' PDF : 65 Pages View PDF
EclipsePlus Family Data Sheet Rev. A
Symbol
Standard Input
Delays
tSID (LVTTL)
tSID (LVCMOS2)
tSID (GTL+)
tSID (SSTL3)
tSID (SSTL2)
Table 11: Standard Input Delays
Parameter
To get the total input delay add this delay to tISU
LVTTL input delay: Low Voltage TTL for 3.3 V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
Figure 16: EclipsePlus Input Register Cell Timing
R
CLK
D
tISU
t IHL
Q
tICO
tIRST
E
tIESU tIEH
Value (ns)
Min. Max.
-
0.34
-
0.42
-
0.68
-
0.55
-
0.61
16
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