QL7160-4PB516I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7160-4PB516I' PDF : 65 Pages View PDF
EclipsePlus Family Data Sheet Rev. A
Figure 10: Global Clock Structure Schematic
Programmable Clock
Global Clock Buffer
External Clock
Global Clock
tPGCK
Clock
Select
tBGCK
Figure 11: RAM Module
[9:0]
[17:0]
WA
RE
WD
WE
WCL K
RCLK
[9:0]
RA
[17:0]
RD
ASYNCRD
RAM Module
Symbol
tSWA
tHWA
tSWD
tHWD
tSWE
tHWE
tWCRD
Table 8: RAM Cell Synchronous Write Timing
Parameter
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
Value (ns)
Min.
Max.
0.675 ns
-
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
0 ns
-
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
0.654 ns
-
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
0 ns
-
WE setup time to WCLK: time the WRITE ENABLE must be stable before the
active edge of the WRITE CLOCK
0.276 ns
-
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
0 ns
-
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
-
2.796
ns
12
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