QL7160-4PT208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7160-4PT208C' PDF : 45 Pages View PDF
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7DEOH summarizes the key signals in QuickLogic’s PLLs.
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PLLCLK_IN Input clock signal
PLL_RESET
Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted and then released in
order for the LOCK_DETECT to work.
ONn_OFFCHIP
PLL output This signal selects whether the PLL will drive the internal clock
network or be used off-chip. This is a static signal, not a dynamic signal.
Tied to GND = outgoing signal drives internal gates.
Tied to VCC = outgoing signal used off-chip.
Out to internal gates This signal bypasses the PLL logic before driving the
CLKNET_OUT internal gates. Note that this signal cannot be used in the same quadrant where
the PLL signal is used (PLLCLK_OUT).
PLLCLK_OUT
Out from PLL to internal gates This signal can drive the internal gates after
going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND.
PLLPAD_OUT
Out to off-chip This outgoing signal is used off-chip. For this to work,
ONn_OFFCHIP signal must be tied to VCC.
Active High Lock detection signal NOTE: For simulation purposes, this
LOCK_DETECT signal gets asserted after 10 clock cycles. However, it can take a maximum of
200 clock cycles to sync with the input clock upon release of the RESET signal.
NOTE: Because PLLCLK_IN and PLL_RESET signals have INPAD, and PLLPAD_OUT has
OUTPAD, you do not have to add additional pads to your design
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