QL8025-7PF144M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL8025-7PF144M
QuickLogic Corporation
'QL8025-7PF144M' PDF : 49 Pages View PDF
(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY %
5HFRPPHQGHG 8QXVHG 3LQ 7HUPLQDWLRQV IRU WKH (FOLSVH,,
'HYLFHV
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally
using the Configuration Editor. This option is given in the bottom-right corner of the placement
window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-
down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in 7DEOH .
6LJQDO 1DPH
PLLOUT<x>a
IOCTRL<y>b
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
7DEOH 5HFRPPHQGHG 8QXVHG 3LQ 7HUPLQDWLRQV
5HFRPPHQGHG 7HUPLQDWLRQ
Unused PLL output pins must be connected to either VCC or GND so that their associated
input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the
chip should not be tied to either VCC or GND.
There is an internal pulldown resistor to Ground on this pin. This pin should be tied to
Ground if it is not used. For backwards compatibility with Eclipse, it can be tied to Vcc or
Ground. If tied to Vcc, it will draw no more than 20 µA per IOCTRL pin due to the pulldown
resistor.
Any unused clock pins should be connected to VCC or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC,
under normal operation use it as needed.
If an I/O bank does not require the use of INREF signal the pin should be connected to
GND.
a. x represents a number.
b. y represents an aphabetical character.
34)3 3LQRXW 'LDJUDP
Eclipse-II
QL8325-7PQ208C
Preliminary 4XLFN/RJLF &RUSRUDWLRQ
ZZZTXLFNORJLFFRP
Share Link: 