QL8025-8PV100I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL8025-8PV100I

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tSWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the

active edge of the WRITE CLOCK

tHWA

WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active

edge of the WRITE CLOCK

tSWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active

edge of the WRITE CLOCK

tHWD

WD hold time to WCLK: time the WRITE DATA must be stable after the active edge

of the WRITE CLOCK

tSWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active

edge of the WRITE CLOCK

tHWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active

edge of the WRITE CLOCK

tWCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the

time when the data is available at RD

9DOXH

0LQ

0D[

0.675 ns

-

0 ns

-

0.654 ns

-

0 ns

-

0.623 ns

-

0 ns

-

-

4.38 ns

WCLK

WA

tSWA

tHWA

WD

tSWD

tHWD

WE

tSWE

tHWE

RD

old data

new data

tWCRD

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