QL8050-7PT280C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL8050-7PT280C

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

Prev 11 12 13 14 15 16 17 18 19 20 Next

(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY %

Quad Net

Global Clock Net

GCLK Pin

)LJXUH  *OREDO &ORFN $UFKLWHFWXUH

4XDG1HW 1HWZRUN

There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device.

Each Quad-Net is local to a quadrant. Before driving the columns clock buffers, the quad-net is

driven by the output of a mux which selects between the GCLK input and an internally generated

clock source (see )LJXUH ).

Internally generated clock, or

clock from general routing network

Global Clock

(GCLK) Input

Global Clock Network

FF

tPGCK

tBGCK

Global Clock Buffer

)LJXUH  *OREDO &ORFN 6WUXFWXUH 6FKHPDWLF



‡‡‡‡‡‡ ZZZTXLFNORJLFFRP

Preliminary ‹  4XLFN/RJLF &RUSRUDWLRQ

Share Link: