QL8150-8PS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL8150-8PS484M

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

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tISU

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tSID

PAD

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tISU

Input register setup time: time the synchronous input of the flip-flop must be stable

before the active clock edge

2.50 ns

-

tIHL

Input register hold time: time the synchronous input of the flip-flop must be stable

after the active clock edge

-

0 ns

tICO

Input register clock-to-out: time taken by the flip-flop to output after the active clock

edge

- 1.08 ns

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