QL82SD-5PQ208I View Datasheet(PDF) - QuickLogic Corporation
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MFG CO.
'QL82SD-5PQ208I' PDF : 60 Pages View PDF
QL82SD Device Data Sheet Rev C
ECU Block Description
ECU Block General Description
Traditional Programmable Logic architectures do not implement arithmetic functions
efficiently or effectively. These functions require high logic cell usage while garnering only
moderate performance results. By embedding a dynamically reconfigurable computational
unit, the QuickSD device can address various arithmetic functions efficiently and effectively
providing for a robust DSP platform—this approach offers greater performance than
traditional programmable logic implementations. The ECU block is ideal for complex DSP,
filtering, and algorithmic functions. The QuickSD device architecture will allow functionality
above and beyond that achievable using DSP processors or programmable logic devices. The
embedded block is implemented at the transistor level with the following block diagram.
Abus
Xbus
Ybus
Ibus
Sign
88
Multiply
16
8
8
16 16
Add
Register
3
1
17
Rbus
Sequencer Memory Logic Cell
Figure 48: SERDES ECU Block Diagram
ECU Mode Select
Table 31: Instruction Set Sequencer
Instruction Set
Operation
0
0
0
Multiply
0
0
1
Multiply - Add
0
1
0
Accumulate
0
1
1
Add
1
0
0
Multiply (registered) a
1
0
1
Multiply - Add (registered)
1
1
0
Multiply Accumulate
1
1
1
Add (registered)
a. A[15:0] set to zero.
The ECU block can be configured for eight arithmetic functions via an instruction as shown
in Table 31. The modes for the ECU block are Dynamically Re-programmable through the
Instruction Set Sequencer.
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