QL901M-6PS680C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M-6PS680C' PDF : 37 Pages View PDF
Table 27: Pin Descriptions (Continued)
Pin
I/O
Function
CPU_BIGENDIAN
I
Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates
little-endian byte ordering.
CPU_EXTINT_n<6:0>
I CPU Interrupts. Asserting Low any of these inputs causes an interrupt to the QuickMIPS chip.
PL_BYPASS
I
PLL Bypass. When High, the 2X multiplication of the input clock is not performed and the output clocks
are half their normal frequencies.
PL_CLKOUT
O Output Clock from PLL.
PL_CLOCKIN
I Input Clock to PLL.
PL_ENABLE
PLL Enable. A High assertion of this signal powers down the PLL when it is not being used to reduce
I
overall device power and puts the QuickMIPS chip into a quiescent current testing mode. When
PL_ENABLE is Low, the PLL is not functional, but the clock outputs can be used if the PL_BYPASS
input is High.
PL_LOCK
O
PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid
output clocks.
PL_RESET_n
I PLL Reset.
PL_WARMRESET_n
I PLL Warm Reset.
STM
I QuickLogic Reserved pin. Tie to GND on the PCB.
Power and Ground Signals
GND
I Ground pin. Tie to GND on the PCB.
GNDPLL
I Ground for the PLL.
VCCIO
I
Supply pin for I/O. Set to 2.5V for 2.5V I/O, 3.3V for 3.3V compliant I/O, or refer to the I/O Standards
table.
VCCIO<A:D>
I VCCIO port for each of the four I/O banks.
VCCPLL
I Supply for the PLL.
VCC
I Supply pin. Tie to 2.5V supply.
(Sheet 6 of 6)
QuickLogic device
QuickMIPS device part
number
Speed Grade
6 = Faster
QL 901M- 6 PS680 C
Operating Range
C = Commercial
I = Industrial
Package Code
PS680 = 680-pin BGA (1.0mm)
Figure 26: Ordering Information
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32
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© 2001 QuickLogic Corporation
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