QL901M-6PS680C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M-6PS680C' PDF : 37 Pages View PDF
4.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=0.74)
The AC Specifications, Logic Cell diagrams, and waveforms are provided below.
Figure 4: QuickMIPS Logic Cell
Table 5: Logic Cells
Symbol
Parameter
Logic Cells
tPD Combinatorial delay: time taken by the combinatorial circuit to output
tSU
Setup time: the amount of time the synchronous input of the flip flop must be stable before
the active clock edge
thl
Hold time: the amount of time the synchronous input of the flip flop must be stable after the
active clock edge
tCLK
Clock to out delay: the amount of time the synchronous input of the flip flop must be stable
after the active clock edge
tCWHI Clock High Time: the length of time that the clock stays high
tCWLO Clock Low Time: the length of time that the clock stays low
tSET
Set Delay: amount of time between when the flip flop is “set” (high)
and when Q is consequent “set” (high)
tRESET
Reset Delay: amount of time between when the flip flop is “reset” (low) and when Q is
consequent “reset” (low)
tSW
Set Width: length of time that the SET signal remains high
(low if active low)
tRW
Reset Width: length of time that the RESET signal remains high
(low if active low)
Propagation
delay (ns)
0.257
0.22
0
0.255
0.46
0.46
0.18
0.09
0.3
0.3
•
8
•
•
www.quicklogic.com
•
•
•
© 2001 QuickLogic Corporation
Share Link: 
