RC28F128J3D095 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F128J3D095' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
9.7.6
Locking the OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. Bit 1 is set using the Protection
Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Figure 18: Protection Register Memory Map
Word
Address
A[24:1]: 256 Mbit A[22:1]: 64 Mbit
A[23:1]: 128 Mbit A[21:1]: 32 Mbit
0x88
64-bit Segment
0x85
0x84
(User-Programmable)
128-Bit Protection Register 0
64-bit Segment
0x81
(Factory-Programmed)
Lock Register 0
0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note: A0 is not used in x16 mode when accessing the protection register map. See Table 29 for x16 addressing. In x8 mode
A0 is used, see Table 30 for x8 addressing.
Table 29: Word-Wide Protection Register Addressing
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
Both
1
0
0
0
0
0
0
0
0
Factory
1
0
0
0
0
0
0
1
1
Factory
1
0
0
0
0
0
1
0
2
Factory
1
0
0
0
0
0
1
1
3
Factory
1
0
0
0
0
1
0
0
4
User
1
0
0
0
0
1
0
1
5
User
1
0
0
0
0
1
1
0
6
User
1
0
0
0
0
1
1
1
7
User
1
0
0
0
1
0
0
0
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
December 2007
316577-06
Datasheet
45
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