RC28F256J3D095 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F256J3D095' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
8.1
8.1.1
8.1.1.1
Bus Reads
Reading from flash memory outputs stored information to the processor or chipset, and
does not change any contents. Reading can be performed an unlimited number of
times. Besides array data, other types of data such as device information and device
status is available from the flash.
To perform a bus read operation, CEx (refer to Table 16 on page 31) and OE# must be
asserted. CEx is the device-select control; when active, it enables the flash memory
device. OE# is the data-output control; when active, the addressed flash memory data
is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See
Section 9.2, “Read Operations” on page 37.
Asynchronous Page Mode Read
There are two Asynchronous Page mode configurations available on Numonyx™
Embedded Flash Memory (J3 v D, Monolithic) , depending on the system design
requirements:
• Four-Word Page mode: This is the default mode on power-up or reset. Array data
can be sensed up to four words (8 Bytes) at a time.
• Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a
time. This mode must be enabled on power-up or reset by using the command
sequence described in Table 19 on page 35. Address bits A[3:1] determine which
word is output during a read operation, and A[3:0] determine which byte is output
for a x8 bus width.
After the initial access delay, the first word out of the page buffer corresponds to the
initial address. In Four-Word Page mode, address bits A[2:1] determine which word is
output from the page buffer for a x16 bus width, and A[2:0] determine which byte is
output from the page buffer for a x8 bus width. Subsequent reads from the device
come from the page buffer. These reads are output on D[15:0] for a x16 bus width and
D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page
mode) or A[3:0] (Eight-Word Page mode).
Data can be read from the page buffer multiple times, and in any order. In Four-Word
Page mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at
any time, or if CEx# is toggled, the device will sense and load new data into the page
buffer. Asynchronous Page mode is the default read mode on power-up or reset.
To perform a Page mode read after any other operation, the Read Array command must
be issued to read from the flash array. Asynchronous Page mode reads are permitted in
all blocks and are used to access register information. During register access, only one
word is loaded into the page buffer.
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile storage register that when
addressed by the Set ECR command can select between Four-Word Page mode and
Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when
RP# is deasserted or power is removed from the device. To modify ECR settings, use
the Set ECR command. The Set ECR command is written along with the configuration
register value, which is placed on the lower 16 bits of the address bus A[15:0]. This is
followed by a second write that confirms the operation and again presents the ECR data
on the address bus. After executing this command, the device returns to Read Array
mode.
The ECR is shown in Table 17. 8-word page mode Command Bus-Cycle is captured in
Table 18.
Datasheet
32
December 2007
316577-06
Share Link: 
