RC28F256J3D095 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F256J3D095' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 27: STS Configuration Coding Definitions
D7
D6
D5
D4
D3
D2
D1
D0
Reserved3
Pulse on
Program
Complete
(1)
Pulse on
Erase
Complete
(1)
D[1:0] = STS Configuration Codes
Notes
00 = default, level mode;
device ready indication
Controls HOLD to a memory controller to prevent accessing a flash memory
subsystem while any flash device's WSM is busy.
01 = pulse on Erase Complete
Generates a system interrupt pulse when any flash device in an array has
completed a block erase. Helpful for reformatting blocks after file system free
space reclamation or “cleanup.”
10 = pulse on Program Complete
Not supported on this device.
11 = pulse on Erase or Program Complete
Generates system interrupts to trigger servicing of flash arrays when either
erase or program operations are completed, when a common interrupt service
routine is desired.
Notes:
1.
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
2.
An invalid configuration code will result in both SR.4 and SR.5 being set.
3.
Reserved bits are invalid should be ignored.
9.7
Security and Protection
Numonyx™ Embedded Flash Memory (J3 v D) device offer both hardware and software
security features. Block lock operations, PRs and VPEN allow users to implement
various levels of data protection.
9.7.1
Normal Block Locking
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic) has the unique capability of
Flexible Block Locking (locked blocks remain locked upon reset or power cycle): All
blocks are unlocked at the factory. Blocks can be locked individually by issuing the Set
Block Lock Bit command sequence to any address within a block. Once locked, blocks
remain locked when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed. Table 28 summarizes the command bus-cycles.
Table 28: Block Locking Command Bus-Cycles
Command
Set Block Lock Bit
Clear Block Lock Bits
Setup Write Cycle
Address Bus
Block Address
Device Address
Data Bus
0060h
0060h
Confirm Write Cycle
Address Bus
Block Address
Device Address
Data Bus
0001h
00D0h
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when VCC and VPEN
are valid. When VPEN ≤ VPENLK, block lock-bits cannot be changed.
December 2007
316577-06
Datasheet
43
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