RC28F256J3D95 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F256J3D95' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention
Figure 7: Timing Signal Naming Convention
t E LQV
Source Signal
Source State
Target State
Target Signal
Figure 8: Timing Signal Name Decoder
Signal
Code
Address
A
Data - Read
Q
Data - Write
D
Chip Enable (CE)
E
Output Enable (OE#)
G
Write Enable (WE#)
W
Address Valid (ADV#)
V
Reset (RP#)
P
Clock (CLK)
C
WAIT
T
High
Low
High-Z
Low-Z
Valid
Invalid
State
Code
H
L
Z
X
V
I
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s
data sheet, and is the address-to-data delay for subsequent page-mode reads.
7.1
Read Specifications
Table 10: Read Operations (Sheet 1 of 2)
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Density
Min
Max
Unit
R1
tAVAV
Read/Write Cycle Time
32 Mbit
75
64 Mbit
75
ns
128 Mbit
75
256 Mbit
95
Notes
1,2
1,2
1,2
1,2
December 2007
316577-06
Datasheet
23
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