RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
RC28F320J3F75
Micron Technology
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 44: Protection Register Information
Offset(1)
P = 31h
Length
Description
(Optional Flash Features and Commands)
(P+E)h
1
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits 0-15 point
to the protection register lock byte, the section’s first byte. The
4
following bytes are factory pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
Note:
1.
The variable P is a pointer which is defined at CFI offset 15h.
Add.
3F:
40:
41:
42:
43:
Hex
Code
--01
--80
--00
--03
--03
Value
01
80h
00h
8bytes
8bytes
Table 45: Burst Read Information
Offset(1)
P = 31h
Length
Description
(Optional Flash Features and Commands)
(P+13)h
Page Mode Read capability
1
bits 0–7 = “n” such that 2n HEX value represents the number of read-
page bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
(P+14)h
1
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
(P+15)h
Synchronous Mode Read Capability Configuration 1
Bits 3-7 = Reserved
bits 0-2 = “n” such that 2n+1 HEX value represents the maximum
number of continuous synchronous burst reads when the device is
configured for its maximum word width. A value of 07h indicates that
1
the device is capable of continuous linear bursts until that will output
data until the internal burst counter reaches the end of the device’s
burstable address space. This field’s 3-bit value can be written directly
to the Read Configuration Register Bits 0-2 if the device is configured for
its maximum word width. See offset 1Fh for word width to determine
the burst data output width.
(P+16h)h
1
Synchronous Mode Read Capability Configuration 2
(P+45h)h
1
J3C mark for VIL fix for customers
Note:
1.
The variable P is a pointer which is defined at CFI offset 15h.
Add.
44:
45:
46:
47:
76:
Hex
Code
Value
--04 16 byte
--00
0
--00
n/a
--00
n/a
--01
01
Jan 2011
208032-03
Datasheet
63
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