RC28F640J3D75 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F640J3D75' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 3:
Symbol
D[15:8]
CE[2:0]
RP#
OE#
WE#
STS
BYTE#
VPEN
VCC
VCCQ
GND
NC
RFU
Signal Descriptions for Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
(Sheet 2 of 2)
Type
Name and Function
Input/
Output
Input
Input
Input
Input
Open Drain
Output
Input
Input
Power
Power
Supply
—
—
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLE: Activate the 32-, 64-, 128-, and 256-Mbit devices’ control logic, input buffers,
decoders, and sense amplifiers. When the device is de-selected (see Table 16, “Chip Enable
Truth Table for 32-, 64-, 128- and 256-Mb” on page 31), power reduces to standby
levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for
32-, 64-, 128- and 256-Mb” on page 31).
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and Section 9.6, “Status Signal” on page 42. STS is to be tied
to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
≤ Vlko.
Caution: Device operation at invalid Vcc voltages should not be attempted.
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC.
GROUND: Ground reference for device logic voltages. Connect to system ground.
No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
December 2007
316577-06
Datasheet
17
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