Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 10: Read Operations (Sheet 2 of 2)
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
R2
tAVQV
Address to Output Delay
R3
tELQV
CEX to Output Delay
R4
tGLQV
OE# to Non-Array Output Delay
R5
tPHQV
RP# High to Output Delay
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
CEX to Output in Low Z
OE# to Output in Low Z
CEX High to Output in High Z
OE# High to Output in High Z
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
tELFL/tELFH
tFLQV/tFHQV
tFLQZ
tEHEL
tAPA
CEX Low to BYTE# High or Low
BYTE# to Output Delay
BYTE# to Output in High Z
CEx High to CEx Low
Page Address Access Time
tGLQV
OE# to Array Output Delay
Density
32 Mbit
64 Mbit
128 Mbit
256 Mbit
32 Mbit
64 Mbit
128 Mbit
256 Mbit
All
32 Mbit
64 Mbit
128 Mbit
256 Mbit
All
All
All
Min
0
0
0
0
Max
75
75
75
95
75
75
75
95
25
150
180
210
210
25
15
10
1
1
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2,4
1,2
1,2
1,2
1,2
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2
1,2,5
1,2,5
5, 6
1,2,4
Notes:
1.
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined as the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31).
2.
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3.
OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 16,
“Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31) without impact on tELQV.
4. See Figure 15, “AC Input/Output Reference Waveform” on page 30 and Figure 16, “Transient
Equivalent Testing Load Circuit” on page 30 for testing characteristics.
5.
Sampled, not 100% tested.
6.
For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Datasheet
24
December 2007
316577-06