RDD104 View Datasheet(PDF) - LSI Computer Systems
Part Name
Description
MFG CO.
'RDD104' PDF : 2 Pages View PDF
1
2
DYNAMIC ELECTRICAL CHARACTERISTICS:
(CL = 50pF, Input Rise and Fall Times = 20ns except for Clock,
unless otherwise specified.)
VDD MIN MAX
Clock Input Frequency
4.5V
0
1.5
10V
0
4.0
15V
0
6.0
UNIT
MHz
MHz
MHz
Clock Input Rise & Fall Times 4.5 to 15V - No Limit
Clock Input Rise & Fall Time,
CL = 15pF
4.5V -
140
ns
10V
-
70
ns
Clock Output Propagation
Delay, CL = 15pF
4.5V -
300
ns
10V -
150
ns
Output Rise & Fall Times
4.5V -
400
ns
10V -
200
ns
Propagation Delay to Output
4.5V -
1500
ns
10V -
750
ns
Reset Pulse Width
4.5V 800
-
ns
10V 400
-
ns
Reset Removal Time
4.5V -
500
ns
10V -
250
ns
Reset Propagation Delay
to Output
4.5V -
1400
ns
10V -
700
ns
Select Input Setup Time
4.5V -
800
ns
10V -
400
ns
PIN 5
10M
PIN 6
FIGURE 2.
MINIMUM PARTS OSCILLATOR CIRCUIT
PIN 5
100pF
20M
40pF
10M
PIN 6
FIGURE 3.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW
PIN 5
50pF
10M
20pF
56pF
39pF
PIN 6
FIGURE 4.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ
CLOCK
INPUT
SIGNAL
R1
5
V DD
V DD
FIGURE 5. TYPICAL INPUT
If input signals are less than VSS or greater than
VDD, a series input resistor, R1, should be used to
limit the maximum input current to 2 milliamperes.
CLOCK IN
5
OSCILLATOR
EXTERNAL
COMPONENTS
V SS
3 STAGE INVERTING
AMPLIFIER
FIGURE 6.
RDD 104 BLOCK DIAGRAM
+V
8 V DD
-V
3 V SS
R
CLOCK
GENERATOR
÷ 10
÷ 10
÷ 10
÷ 10
CLOCK OUT
6
RESET 4
DIVIDER SELECT-1 1
DIVIDER SELECT-2 2
RDD104-011000-2
DECODER
1 OUT OF 4 SELECTOR
BUFFER
7 OUTPUT
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