RIVA128ZX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'RIVA128ZX' PDF : 85 Pages View PDF
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
9 BOOT ROM INTERFACE
BIOS and initialization code for the RIVA128ZX is accessed from a 32KByte ROM. The RIVA128ZX mem-
ory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes of
data respectively. The unique decode to the ROM device is provided by the ROMCS# chip select signal.
Figure 63. ROM interface
RIVA128ZX
ROMCS#
FBD[15:0]
FBD[31:24]
FBD[17]
FBD[16]
CS
A[15:0]
D[7:0]
WE
OE
ROM
ROM interface timing specification
Figure 64. ROM interface timing diagram
ROM Read
FDB[15:0]
ROMCS#
tBAS
OE# (FBD[16])
WE# (FBD[17])
tBOS
tBRV
FDB[31:24]
tBDBZ
address
tBRCS
tBAH
tBRCA
tBOH
tBRH
tBDS
data
tBDZ
tBDH
FDB[15:0]
ROMCS#
OE# (FBD[16])
WE# (FBD[17])
FDB[31:24]
ROM Write
tBAS
address
tBRCS
tBAH
tBWS
tBWL
tBWDS
data
tBWDH
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