RS8953SPBEPF View Datasheet(PDF) - Conexant Systems
Part Name
Description
MFG CO.
'RS8953SPBEPF' PDF : 173 Pages View PDF
RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.13 Receive/Transmit Status
4.13 Receive/Transmit Status
Base Address
HDSL Channel 1 (CH1)
0x00
HDSL Channel 2 (CH2)
0x08
HDSL Channel 3 (CH3)
0x10
Table 4-10. Receive and Transmit Status Read Registers
CH1 CH2 CH3 Register Label Bits
Register Description
0x00 0x08 0x10
0x01 0x09 0x11
0x02 0x0A 0x12
0x03 0x0B 0x13
0x04 0x0C 0x14
0x18
0x19
0x1A
0x1B
0x1C
0x05 0x0D 0x15
0x06 0x0E 0x16
0x07 0x0F 0x17
0x21 0x29 0x31
0x22 0x2A 0x32
REOC_LO
REOC_HI
RIND_LO
RIND_HI
RZBIT_1
RZBIT_2
RZBIT_3
RZBIT_4
RZBIT_5
RZBIT_6
STATUS_1
STATUS_2
STATUS_3
CRC_CNT
FEBE_CNT
8 Receive EOC Bits
8 Receive EOC Bits
8 Receive IND Bits
8 Receive IND Bits
8 Receive Z-bits
8 Common Receive Z-bits (CHn = ZBIT_SEL)
8 Common Receive Z-bits (CHn = ZBIT_SEL)
8 Common Receive Z-bits (CHn = ZBIT_SEL)
8 Common Receive Z-bits (CHn = ZBIT_SEL)
8 Common Receive Z-bits (CHn = ZBIT_SEL)
8 Receive Status
8 Receive Status
8 Transmit Status
8 CRC Error Count
8 Far-End Block Error Count
The MPU may read all receive and transmit status registers non-destructively at any time. All status registers are
updated coincident with their respective HDSL channel’s receive or transmit 6 ms frame interrupts indicated in
the Interrupt Request Register [IRR; addr 0x1F]. Therefore, the MPU may poll the IRR or enable interrupts to
determine whether a status update has occurred. Real-time receive status (REOC, RIND, and RZBIT) register
updates are suspended when the respective HDSL channel’s receive framer reports an OUT_OF_SYNC state
[STATUS_1; addr 0x05].
0x00—Receive Embedded Operations Channel (REOC_LO)
7
6
5
4
3
2
1
0
REOC[7:0]
N8953BDSB
Conexant
4-53
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