S39421 View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
'S39421' PDF : 28 Pages View PDF
S39421
The board’s pins should now be mated with the backplane
connector which in turn will bring the host LI/I* and
RESET* signals to the S39421. These signals should be
tied to the device’s HST_PWR and HST_RST inputs
respectively. Whenever HST_PWR is low the outputs
controlling the backend power on sequencing will be
inhibited; it does not impact the reset outputs or reset
timer. When low, the HST_RST input will force the reset
outputs active; once it is released the reset timer will be
started and it will keep the reset outputs active for tPURST.
At the same time the signal pins are making contact, the
backend voltages are applied to the card (3.3V, 5V, +12V
and -12V on short pins), but, they are blocked by FETs
under the control of the S39421 (see figure 3 ). Depending
upon the state of the VSEL pin, the S39421 will monitor
either the bussed +5V only, the bussed +3.3V only or both
the bussed +5V and +3.3V. Once the S39421 has deter-
mined these supply voltages are at or above Vtrip, (and LI/
I* has released HST_PWR) it will release the VGATE
outputs and effectively turn them on at a rate equivalent
to 250V/second. At the same time it will force DRVREN
active thus providing power to the backend circuits.
Vpc
Gnd
System
Vcc
IL/I*
RESET*
LI/O*
Ejector Switch
Circuit
VCC5 PND1
HST_PWR
HST_RST
SGNL_VLD
S39421
DRVREN
VGATE3
VGATE5
CARD3V
CARD5V
RESET
RESET
Backend
Power Circuits
See Figure
Backend Voltage
to S39421
Monitor Circuits
Reset Control
of Backend
Circuits
Gnd
Vpc
2024 ILL28.0
FIGURE 25: GENERAL BLOCK DIAGRAM OF S39421 HOST BUS INTERFACE AND BACKEND SIGNAL INTERFACE
2024 9.0 8/8/00
22
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