S3C9454B View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'S3C9454B' PDF : 199 Pages View PDF
SAM88RCRI INSTRUCTION SET
S3C9454B/F9454B
ADD — Add
ADD
Operation:
dst,src
dst ← dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is
of the opposite sign; cleared otherwise.
Format:
opc dst | src
Bytes
2
Cycles
4
6
Opcode
(Hex)
02
03
Addr Mode
dst src
r
r
r
lr
opc
src
dst
3
6
6
04
R
R
05
R
IR
opc
dst
src
3
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD
ADD
ADD
ADD
ADD
R1,R2
→
R1,@R2 →
01H,02H →
01H,@02H →
01H,#25H →
R1 = 15H, R2 = 03H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register
R1.
6-12
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