S9S08LG16J0VLF View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'S9S08LG16J0VLF' PDF : 50 Pages View PDF
Electrical Characteristics
2.11.3 SPI Timing
Table 16 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
Table 16. SPI Timing
No. C
Function
— D Operating frequency
Master
Slave
1
D SPSCK period
Master
Slave
2
D Enable lead time
Master
Slave
3
D Enable lag time
Master
Slave
4
D Clock (SPSCK) high or low time
Master
Slave
5
D Data setup time (inputs)
Master
Slave
6
D Data hold time (inputs)
Master
Slave
7
D Slave access time
8
D Slave MISO disable time
9
D Data valid (after SPSCK edge)
Master
Slave
10
D Data hold time (outputs)
Master
Slave
11
D Rise time
Input
Output
D Fall time
12
Input
Output
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
tHI
ta
tdis
tv
tHO
tRI
tRO
tFI
tFO
Min
fBus/2048
0
2
4
1/2
1
1/2
1
tcyc – 30
tcyc – 30
15
15
0
25
—
—
—
—
0
0
—
—
—
—
Max
fBus/2
fBus/4
2048
—
—
—
—
—
1024 tcyc
—
—
—
—
—
1
1
25
25
—
—
tcyc – 25
25
tcyc – 25
25
Unit
Hz
tcyc
tcyc
tSPSCK
tcyc
tSPSCK
tcyc
ns
ns
ns
ns
ns
ns
tcyc
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
31
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