S9S08SG32E1VTJ View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'S9S08SG32E1VTJ' PDF : 328 Pages View PDF
ADCH
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Chapter 8 Analog-to-Digital Converter (S08ADC10V1)
Table 9-4. Input Channel Select (continued)
Input Select
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADCH
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Input Select
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
Reserved
VREFH
VREFL
Module disabled
9.3.2 Status and Control Register 2 (ADCSC2)
The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC
module.
7
6
5
4
3
R ADACT
0
ADTRG
ACFE
ACFGT
W
Reset:
0
0
0
0
0
= Unimplemented or Reserved
2
1
0
0
R1
R1
0
0
0
1 Bits 1 and 0 are reserved bits that must always be written to 0.
Figure 9-4. Status and Control Register 2 (ADCSC2)
Table 9-5. ADCSC2 Register Field Descriptions
Field
7
ADACT
6
ADTRG
Description
Conversion Active — Indicates that a conversion is in progress. ADACT is set when a conversion is initiated
and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
Conversion Trigger Select — Selects the type of trigger used for initiating a conversion. Two types of triggers
are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated
following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion
of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected
MC9S08SG32 Data Sheet, Rev. 7
Freescale Semiconductor
119
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