S9S08SG32E1VTJ View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'S9S08SG32E1VTJ' PDF : 328 Pages View PDF
Chapter 2 Pins and Connections
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
The MC9S08SG32 Series devices contain a ganged output drive feature that allows a safe and reliable
method of allowing pins to be tied together externally to produce a higher output current drive. See Section
6.3, “Ganged Output” for more information for configuring the port pins for ganged output drive.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused pins to outputs so they do not float.
When using the 20-pin devices, either enable on-chip pullup devices or
change the direction of non-bonded PTC7-PTC4 and PTA7-PTA6 pins to
outputs so the pins do not float.
When using the 16-pin devices, either enable on-chip pullup devices or
change the direction of non-bonded out PTC7-PTC0 and PTA7-PTA6 pins
to outputs so the pins do not float.
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
Lowest
Priority
Highest
28-pin 20-pin1 16-pin Port Pin
Alt 1
Alt 2
1
—
— PTC5
2
—
— PTC4
3
1
1
4
2
2
5
6
3
3
7
8
4
9
5
10
6
11
7
12
8
4
5 PTB7
6 PTB6
7 PTB5
8 PTB4
SCL3
SDA3
TPM1CH14
TPM2CH16
EXTAL
XTAL
SS
MISO
13
9
— PTC3
14
10
— PTC2
15
11
— PTC1
16
12
— PTC0
TPM1CH14
TPM1CH04
17
13
9 PTB3
PIB3
MOSI
18
14
10 PTB2
PIB2
SPSCK
Alt 3
PTC05
PTC05
PTC05
PTC05
PTC05
PTC05
PTC05
PTC05
Alt 4
BKGD
VDDA
VSSA
ADP11
ADP10
ADP9
ADP8
ADP7
ADP6
Alt 5
ADP13
ADP12
RESET2
MS
VDD
VREFH
VREFL
VSS
MC9S08SG32 Data Sheet, Rev. 7
28
Freescale Semiconductor
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