SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.5.6 PLL EQUALIZER PRESET REGISTER (PLLEQU)
The function of this register is dependent upon whether its being read or written. Tables 38, 39 and 40 define the register
function for the write operation. Tables 38 and 41 define the register function for the read operation.
Table 38 PLL Equalizer Preset Register (address 03H) - WRITE/READ
7
PLLFreq.1
−
6
PLLFreq.0
−
5
Tap a1.2
−
4
Tap a1.1
−
3
Tap a1.0
−
2
Tap a2.2
LongSymb
1
Tap a2.1
FLock
0
Tap a2.0
InLock
Table 39 Description of PLLEqu bits for write operation
BIT
SYMBOL
DESCRIPTION
7
PLLFreq.1 These 2 bits are the 2 LSBs of the 10-bit PLL frequency code; see Section 7.5.5.
6
PLLFreq.0
5
Tap a1.2 These 3 bits select the equalizer tap setting a1; see Table 40.
4
Tap a1.1
3
Tap a1.0
2
Tap a2.2 These 3 bits select the equalizer tap setting a2; see Table 40.
1
Tap a2.1
0
Tap a2.0
Table 40 Selection of equalizer tap settings: a1 and a2
Tap a1.2
Tap a2.2
0
0
0
0
1
1
X
Tap a1.1
Tap a2.1
0
0
1
1
0
0
X
Tap a1.0
Tap a2.0
0
1
0
1
0
1
X
a1 OR a2 EQUALIZER TAP SETTINGS
0
−0.0625
−0.125
−0.1875
−0.25
−0.3125
All other settings are reserved.
Table 41 Description of PLLEqu bits for read operation
BIT
7 to 3
2
1
0
SYMBOL
−
LongSymb
FLock
InLock
DESCRIPTION
These 5 bits are reserved.
If LongSymb = 1, then a run length of 14 has been detected.
If FLock = 1, then PLL is in inner-lock range.
If Inlock = 1, then PLL is in lock.
2000 Mar 21
25
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