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SBPH400-3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
SBPH400-3
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'SBPH400-3' PDF : 43 Pages View PDF
SBPH400-3
Figure 2.9 Remote confirmation packet format
00
phy_ID
0 0 type(A16) 000
port
000 f c b d ok cmnd
logical inverse of first quadlet
The fields in the remote command and remote confirmation packets are interpreted as shown
in Table 2.4.
Table 2.4 Remote Command and Confirmation packet fields
Field
phy_ID
type
port
f
c
b
d
ok
cmnd
data
Comment
Physical node identifier of the destination of the packet (type = 8)
Physical node identifier of the source of the packet (type = A16)
8 - remote command packet
A16 - remote confirmation packet
Identify the port for the command or confirmation. For values other than 0, 1 and 2, the
SBPH400 always responds with the OK bit set to zero in the confirmation packet.
current value of the Fault bit from SBPH400 register 10012 for the addressed port
current value of the Connected bit from SBPH400 register 10002 for the addressed port
current value of the Bias bit from SBPH400 register 10002 for the addressed port
current value of the Disabled bit from SBPH400 register 10002 for the addressed port
1 if the immediately preceding remote command was accepted by the SBPH400, zero
otherwise
type = 8:-
0 - NOP
1 - Transmit TX_DISABLE_NOTIFY then disable the port
2 - Initiate suspend
4 - Clear the port’s Fault bit
5 - Enable port
6 - Resume port
type = A16:-
The cmnd value from the immediately preceding remote command packet
Current value of the SBPH400 register addressed by the immediately preceding Remote
Access packet (reserved and unimplemented fields and registers are returned as zero).
2.8 Link interface
2.8.1 Overview
The link interface in the SBPH400 operates as described in the IEEE P1394a proposal.
The SBPH400 implements an interface to a single 1394 link layer device, using the pins D[0:7],
Ctl[0:1], LREQ, SClk, LPS and LKON. The interface is scalable, using 2 data bits in parallel
per 100 Mbit/sec. This enables the clock rate of the signals at this interface to remain at 50
MHz.
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