SC1403ITSTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC1403ITSTRT' PDF : 31 Pages View PDF
SC1403
POWER MANAGEMENT
Layout Guidelines
As with any high frequency switching regulator design, a good PCB
layout is very essential in order to achieve optimum noise, effi-
ciency, and stability performance of the converter. Before starting
PCB layout, a careful layout strategy is strongly recommended.
See the PCB layout in the SC1403 Evaluation Kit manual for
example. In most applications, use FR4 with 4 or more layers and
at least 2 ounce copper (for output current up to 6A). Use at least
one inner layer for ground connection. It is always a good practice
to tie signal-ground and power-ground at one single point so that
the signal-ground is not easily contaminated. High current paths
should have low inductance and resistance by making trace widths
as wide as possible and lengths as short as possible. Properly
decouple lines that pull large amounts of current in short periods
of time. The following layout strategy should be used in order to
fully utilize the potential of SC1403.
PRELIMINARY
L
VOUT
C O UT
CSL
R1 R2 C
CSH
S C 1403
A.
Power train arrangement.
Place power train components first. The following figure shows
the recommended power train arrangement. Q1 is the main
switching FET, Q2 is the synchronous Rectifier FET, D1 is the
Schottky diode and L1 is the output inductor. The phase node,
where the source of the upper switching FET and the drain of the
synchronous rectifier meets, switches at very high rate of speed,
and is generally the largest source of common-mode noise in the
converter circuit. It should be kept to a minimum size consistent
with its connectivity and current carrying requirements. Also place
the Schottky diode as close to the phase node as possible to
minimize the trace inductance, therefore reducing the efficiency
loss due to the current ramp-up and down time. This becomes
extremely important when the converter needs to handle high di/
dt requirement. Vias between power components should be used
only when necessary: if vias are required, use multiple vias to
reduce the inter-component impedance, and keep the traces
between vias and power components as short and wide as pos-
sible.
With resistive sensing: minimize the length of current sense signal
traces. Keep them less than 15mm. Use Kelvin connections as
shown below; keep the traces parallel to each other and as close
together as possible.
L
CSH
S C 1403
CSL
R sns
Q1
D1
L1
C.
Gate Drive.
The SC1403 has built-in gate drivers capable of sinking/sourcing
1A pk-pk. Upper gate drive signals are noisier than the lower ones,
so place them away from sensitive analog circuits. Make sure the
lower gate traces are as close as possible to the SC1403 pins,
and make both upper and lower gate traces as wide as possible.
D.
PWM placement (pins) and signal ground island.
Q2
Connect all analog grounds to a separate solid copper island plane,
which connects to the SC1403’s GND pin. This includes REF, FB3,
FB5, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#.
B.
Current Sense.
With DCR sensing: The connections from the RC network to the
inductor should be Kelvin connections directly at the inductor
solder pads. Place the capacitor close to the CSH/CSL pins on
the SC1403, and connect to the capacitor using short direct
traces.
E.
Ground plane arrangement.
There are several ways to tie the different grounds together (ana-
log ground, input power ground, and output power ground). With a
buck topology, the output is quiet compared to the input side. The
output is the best place to tie the analog ground to the power
ground, often through a 0Ω resistor. The input power ground and
the output power ground can be tied together using internal planes.
2004 Semtech Corp.
30
United States Patent No. 6,377,032
www.semtech.com
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