SC2544TSTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC2544TSTRT' PDF : 24 Pages View PDF
SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input
voltage ripple due to the ESR is
∆v ESR
= Resr (1+
δ
2
)Io
.
The peak-to-peak input voltage ripple due to the
capacitor is
∆v C
≈
DIo
Cinfs
,
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2544
operate at 180 degrees from each other. If both step-
down channels in the SC2544 are connected to the
same input rail, the input RMS currents will be reduced.
Ripple cancellation effect of interleaving allows the
use of smaller input capacitors.
When two channels with a common input are
interleaved, the total DC input current is simply the
sum of the individual DC input currents. The combined
input current waveform depends on duty ratio and
the output current waveform. Assuming that the
output current ripple is small, the following formula
can be used to estimate the RMS value of the ripple
current in the input capacitor.
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
If D1<0.5 and D2<0.5, then
ICin ≈ D1Io12 + D2Io22 .
If D1>0.5 and (D1-0.5) < D2<0.5, then
ICin ≈ 0.5Io12 + (D1 − 0.5)(Io1 + Io2 )2 + (D2 − D1 + 0.5)Io22 .
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
ICin ≈ 0.5Io12 + D2 (Io1 + Io2 )2 + (D1 − D2 − 0.5)Io22 .
If D1>0.5 and D2 > 0.5, then
ICin ≈ (D1 + D2 − 1)(Io1 + Io2 )2 + (1− D2 )Io12 + (1− D1)Io22 .
Choosing Power MOSFETs
Main considerations in selecting the MOSFET’s are
power dissipation, MOSFETs cost, and packaging.
Switching losses and conduction losses of the MOSFET’s
are directly related to the total gate charge (C ) and
g
channel on-resistance (Rds(on)). In order to judge the
performance of MOSFET’s, the product of the total
gate charge and on-resistance is used as a figure of
merit (FOM). Transistors with the same FOM follow
the same curve in Figure 8.
50
40
Cg( 100 , Rds )
Cg( 200 , Rds )
Cg( 500 , Rds ) 20
1 00
5
10
15
20
1
Rds
20
On-resistance (mOhm)
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
Figure 8. Figure of Merit curves.
The closer the curve is to the origin, the lower is the
FOM. This means lower switching loss or lower
conduction loss or both. It may be difficult to find
MOSFET’s with both low C and low R . Usually a
g
ds(on
trade-off between Rds(on and Cg has to be made.
MOSFET selection also depends on applications. In
many applications, either switching loss or conduction
loss dominates for a particular MOSFET. For
synchronous buck converters with high input to output
voltage ratios, the top MOSFET is hard switched but
conducts with very low duty cycle. The bottom switch
conducts at high duty cycle but switches at near zero
voltage. For such applications, MOSFET’s with low Cg
are used for the top switch and MOSFET’s with low
R are used for the bottom switch.
ds(on)
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance Rds(on);
b) switching loss due to the switch rise time tr and
fall time tf; and
c) the gate loss due to the gate resistance RG.
2005 Semtech Corp.
13
www.semtech.com
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