SC2596 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC2596' PDF : 13 Pages View PDF
POWER MANAGEMENT
Application Information (Cont.)
Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5.
SC2596
Figure 6: Bode Plot of an all ceramic capacitor application
The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V,
IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase
margins for different output capacitor values and ESR values at designed sourcing and sinking currents in
Figure 7.
Phase Margin vs External ESR
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
10mR
IO=380mA_Soure
Cout=4.7uF
Cout=10uF
Cout=22uF
50mR
100mR
200mohm
120.00
100.00
80.00
60.00
40.00
20.00
0.00
-20.00
-40.00
10mR
IO=380mA_SINK
Cout=4.7uF
Cout=10uF
Cout=22uF
50mR
100mR
200mohm
Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values
Layout guidelines
1) The SOIC8-EDP
pad should be add
package of
when PCB
lSaCyo2u5t9. 6Scoamneimthperormveatlhveiatshearrme arleiqmupireeddatnoceco(θnJnC)escitgnthifeictahnetrlym. aAl
suitable
pad to
thermal
the PCB
ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern.
2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the VREF pin with the
shortest connection trace.
3) To reduce the noise on input power rail for standard SSTL-2 application, a 100µF low ESR capacitor and a 1µF
ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.
4) VTT output copper plane should be as large as possible. A 4.7uF to 10µF capacitor have to be used to
decouple the VTT pin.
5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor
close this vsense pin.
© 2009 Semtech Corp.
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