SC403 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC403' PDF : 32 Pages View PDF
SC403
Applications Information (continued)
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 750mV + 20%
(900mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input
is toggled or VDD is cycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When VFB falls 25% below its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to tri-
state the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switch-
ing and tri-states the DH/DL drivers until VDD rises above
3.0V. An internal POR (Power-On Reset) occurs when VDD
exceeds 3.0V, which resets the fault latch and soft-start
counter to prepare for soft-start. The SC403 then begins a
soft-start cycle. The PWM will shut off if VDD falls below
2.4V.
A minimum 0.1μF capacitor referenced to AGND is
required along with a minimum 1.0μF capacitor refer-
enced to PGND to filter the gate drive pulses. Refer to the
layout guidelines section for component placement
suggestions.
LDO ENL Functions
The ENL input is used to control the internal LDO. When
ENL is low (grounded), the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if EN/PSV and VDD meet the
thresholds.
The ENL pin also acts as the switcher UVLO (under-voltage
lockout) for the VIN supply. The VIN UVLO voltage is pro-
grammable via a resistor divider at the VIN, ENL and AGND
pins.
If the ENL pin transitions from high to low within 2 switch-
ing cycles and is less than 1V, then the LDO will turn off
but the switcher remains on. If the ENL goes below the VIN
UVLO threshold and stays above 1V, then the switcher will
turn off but the LDO remains on. The VIN UVLO function
has a typical threshold of 2.6V on the VIN rising edge. The
falling edge threshold is 2.4V.
LDO Regulator
SC403 has an option to bias the switcher by using an inter-
nal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND. The feedback
pin (FBL) for the LDO is regulated to 750mV (see Figure 9).
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum). In this case, the UVLO
function for the input voltage cannot be used. The table
below summarizes the function of the ENL and EN pins,
with respect to the rising edge of ENL.
VDD
RLDO1
To FBL pin
RLDO2
Figure 9 — LDO Start-Up
The LDO output voltage is set by the following equation.
EN
ENL
LDO status Switcher status
low low, < 0.4V
off
off
high low, < 0.4V
off
on
low high, < 2.6V
on
off
high high, < 2.6V
on
off
low high, > 2.6V
on
off
high high, > 2.6V
on
on
VLDO
750mV
u
¨¨©§1
RLDO1
RLDO2
¸¸¹·
20
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