SC414/SC424
Applications Information (continued)
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
tor. For a conventional PWM constant-frequency con-
verter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essen-
tially constant for a given V and V combination, to
OUT
IN
offset the losses the off-time will tend to reduce slightly as
load increases. The net effect is that switching frequency
increases slightly with increasing load.
lator with a maximum current of 6A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
• IC Decoupling capacitors
• PGND plane
• AGND island
• FB, VOUT, and other analog control signals
• BST, ILIM, and LX
• Capacitors and Current Loops
PCB Layout Guidelines
The optimum layout for the SC414/SC424 is shown in
Figure 15. This layout shows an integrated FET buck regu-
IC Decoupling Capacitors
• A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
2 (V5V) and 3 (AGND).
AGND plane on
inner layer
All components
shown Top Side
PGND
VOUT Plane
on Top layer
RFB1
CFF
RFB2
RES_GND — AGND connects
to PGND close to SC414/SC424
RILIM
Pin 1 marking
SC414/SC424 with
vias for LX, AGND,
VIN
CIN
VIN plane on inner
or bottom layer
COUT
L
PGND on inner
or bottom layer
Figure 15 — PCB Layout
LX plane on inner
or bottom layer
Note: This figure is not
to scale
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