SC4525D View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC4525D' PDF : 21 Pages View PDF
= (VO + VD ) ⋅ (1 − D)
FSW ⋅ L1
C8
=
2
π⋅
6
00
⋅
1
10 3
⋅RC2752==.102⋅.1π210⋅8013⋅61=⋅011−023p31=F⋅
2
2
2
2
.3k
.1 ⋅
1
0
3
= 0.45nF
=)
(VO
2
0+%VAD⋅I)Op⋅(⋅p1FSl−WicDa) tions
Vo =
InfoVrcma(1ti+osn/
GPWM (1 +
(ωCpo)(1n+t.Cs)
s
8/
Rω=EnS2QR Cπ+⋅O6s) 20
0/
ω⋅ 1n2
1
0) 3
⋅ 22.1 ⋅10 3
= 12pF
SC4525D
12 S1W_ C⋅INC=O
IOLT⋅hoeoDpg⋅C(o1oa−ml Dopf)encosamtpioennsGaPtiWoMn≈isGCtAoR⋅
,
RS
shape
tVVhoce=fωr(1epq+≈useRn/1CGcωOyPpW,)M(1(1++s
s
/
RωEnωSQRZC+=Os)R2
1
E/SRωCn2O)
,
response of the converter soAC as to achieve high DC
Oo>=f4Dc⋅IoLDn⋅VItalTblao(IOrNooEEcnhouuAooS⋅cdetclFppu)eRk,lbS)rroaasW+caltcoolocPaoocc8pynWbuonkv⋅irpaslMdFeriintesiSr(ya1dttWnmv.esgtor⋅froolaaCawtdfsammOutigatlhpietancrlttaiuolFfhonirireReCCgro,seria7u5p8SennCr()n===Cted4tcA1s7225oareg)02esnππnLmh5swsF2FCsp0Do1i1PZisinf1o1tw.tihgsTlnRRtshes77otrgeerehf.aseiwinainscnnhtooe(ilnGeRGCrrertC7Pl5(rroAWmRoo===oMsrl=a1pl12≈ioa83ng0(mo..πct5G5mpaAF2u)3pC0C1.iZsrnAml1rRiToefi⋅RnihWfRneg7eatrS) ,
a dominant low-frequency pole FP at
ωp
≈
1
RCO
,
ωZ
=
1
R ESRCO
,
and double poles at half the switching frequency.
Including the voltage divider (R4 and R6), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the current loop is internally closed, Cth8e=re2mπaF1iPn1iRng7
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
task for the loop compensation is to design the voltage is sufficient for voltage loop compensation. As shown in
compensator (C5, R7, and C8).
CONTROLLER AND SCHOTTKY DIODE
Io
CA
Rs
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at FZ1, and a high frequency pole
at FP1. The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
Fig.8: Bode plot of looepxcgeasisnisve phase lag at the loop gain crossover due to the
FB
REF
AACC ==+
-
−−EA2200
⋅⋅
llooVVragcgmp
11 ⋅ PWM
⋅ MODULATOR
GG RR CCAA SS
11
22 ππFFCC CCSWOO
⋅⋅
VVFFBB
VVOOL1
Vo
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
AACC
==
−−
22C500
⋅⋅COllooMPgg
22C888
⋅⋅
11
66..11
⋅⋅
1100
−−33
⋅⋅
22
ππ
⋅⋅
Co
8800
⋅⋅
11
1100 33
R4
⋅⋅ 2222 ⋅⋅1100 −−66
⋅⋅ 1133....003360 == 1155..99ddBB
R7
Resr
R6
RR 77
==
1100 11225500..99
00..2288 ⋅⋅1100
−−33
== 2222..33kk
CC
5F5 i=g=u22rππe
7.
⋅⋅ 11
66Bl⋅⋅o11c00k3311d⋅⋅i22ag22r..11am⋅⋅11o00f33co==n00t..r44o55l nnloFFops
FicnoodnrutarcotCCalcn(o88Vcn==Cev)e22Ltro1ππt,e⋅⋅oor66uu00twtp0p0iuut⋅⋅ht1t1(00cVs11a3w3Op)⋅⋅iat2t2ccr22ahitn..ia1n1sngf⋅⋅ce11erf00rfCeu33Oqn==uacnet11indo22cnpplyoFFianFdSFiWnig, guorRue,tp7thuiest
given by:
VVVV ococ == ((11 ++ ss //GGωωP PppWW))MM((11((11++++ss ss//RRωωEEnnSSQQRR CC ++OOss)) 22 // ωωnn22 ))
(8)
30
0
-30
-60
0.2K
Fz1
Fp1
Fp
COMPENSATOR GAIN
CONVERTER
Fc
GAIN
LOOP GAIN
Fz Fsw/2
2K
20K
200K
2M
FREQUENCY (Hz)
Figure 8. Bode plots for voltage loop design
This transfer function has a finite DC gain
GGPPWWMM
≈≈
RR
GGCCAA ⋅⋅RRSS
,,
ωωpp
≈≈
11
RRCCOO
,,
ωωZZ == RR EESS11RRCCTthOOhe,e, rSeCfo45re2,5tDhecapnrobceesduumremoafritzheedvaosl:tage loop design for
an ESRRRz77er==o11Fgg00ZmmaAA22CC00t
©
2011 Semtech
CC55 ==
C11orp.
(1) Plot the converter gain, i.e. control to feedback transfer
function.
www.semtech.com 13
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