SC453 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC453' PDF : 23 Pages View PDF
SC453
POWER MANAGEMENT
Applications Information (Cont.)
PG# Output
This is an open-drain output and should be pulled up ex-
ternally. This signal is asserted (pulled low) by the SC453
whenever the core voltage is within ±14% of the VID
programmed value. If the chip is disabled or enabled in
UVLO, then PG# is de-asserted. During start-up PG# re-
mains de-asserted until the core voltage has reached the
defined boot voltage and remains there for the BOOT pe-
riod (10μS minimum). This signal is forced low (asserted)
during VID and sleep transitions.
PG_DEL Output
This signal is delayed a minimum of 3mS from first as-
sertion of the PG# signal. This is an open drain output
and should be pulled up externally. This signal is asserted
(open drain) by the SC453 whenever the core is within
±14% of the VID programmed value. If the chip is disabled
or enabled in UVLO, then PG_DEL is de-asserted. The sig-
nal is forced high (open drain) during VID and sleep transi-
tions.
Start-Up and Sequencing
On start-up, VCORE ramps to the boot voltage set by the
BOOTV pin irrespective of the status of the VID pins. After
a minimum of 10μs, PG# asserts, and VCORE responds to
the VID inputs. The controller will then count 1007 switch-
ing cycles before asserting PG_DEL.
Summary of Fault Conditions
Protection Mode
Supply UVLO (VCCA, V5)
32 Cycle Current Limit
114% VCORE OVP
2.0VCORE OVP
Thermal Shutdown
Latched?
When Active
No
Always
Yes SS has terminated and PGDEL is low
Yes SS has terminated and PGDEL is low
Yes
Always
Yes
Always
Driver Status
All low
TG low
BG high
BG high
BG, TG low
SS Pin Status
Low
Sawtooth
High
High
High
Driver Timing Diagram
CMPRF
RCEMFPIN
tpdlTG tfTG
TG
BG
(4)
tpdh tr
BG
BG
(4)
tpdhTG trTG
tpdl
tf
ts pd
BG
BG
Note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is specified from a CMP edge.
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