POWER MANAGEMENT
Pin Configuration
SC483
Ordering Information
Device
SC483ITSTRT(2)
Package(1)
TSSOP-28
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE, RoHS
and J-STD-020B compliant.
TSSOP-28
Pin Descriptions
Pin # Pin Name Pin Function
1
PGND1 Power ground.
2
DL1 Gate drive output for the low side MOSFET switch.
3
VDDP1 +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND1.
4
ILIM1 Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
5
LX1
Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
6
DH1 Gate drive output for the high side MOSFET switch.
7
BST1 Boost capacitor connection for the high side gate drive.
8
EN/PSV2 Enable/Power Save input. Pull down to VSSA2 to shut down OUT2 and discharge it through
22Ω (nom). Pull up to enable OUT2 and activate PSAVE mode. Float to enable OUT2 and activate
continuous conduction mode (CCM), which should be used for dynamic voltage transitioning. If
floated, bypass to VSSA2 with a 10nF ceramic capacitor.
9
TON2 This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET on-
time. Bypass this pin with a 1nF ceramic capacitor to VSSA2.
10
VOUT2 Output voltage sense input for output 2. Connect to the output at the load.
11
VCCA2 Supply voltage input for the analog supply. Use a 10 Ohm / 1uF RC filter from 5VSUS to VSSA2.
12
FB2
Feedback input. Connect to a resistor divider located at the IC from VOUT2 to VSSA2 to set the
output voltage from 0.5V to VCCA2.
13
PGD2 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up.
14
VSSA2 Ground reference for analog circuitry. Connect to PGND2 at the bottom of the output capacitor.
2005 Semtech Corp.
5
www.semtech.com