SC5014 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC5014
Semtech Corporation
'SC5014' PDF : 34 Pages View PDF
SC5014
Definition of Registers and Bits (continued)
Device Control Register
Bit Field Definition Read / Write Description
0x01 [7:6] WIN[1:0]
R/W
A modified duty cycle sent into the PWMI pin replaces the existing saved duty cycle when its
deviation from the saved duty is outside the window for two consecutive samples.
00 = 0 bits (no window)
01 = ±1 bit window
10 = ±2 bit window
11 = ±3 bit window
0x01 [5]
FAST_FREQ R/W
Determines the LED PWM dimming frequency selection:
1 = High PWM dimming frequency mode assuming 9-bit PWM duty cycle dimming, dividing
the system clock 10MHz / (512 x (FREQ+1)).
0 = Low PWM dimming frequency mode assuming 10-bit PWM duty cycle dimming, dividing
the system clock 10MHz / (1024 x (FREQ+1)).
0x01 [4]
FLT_EN
R/W
This bit enables fault checking:
0 = LED_OPEN and LED_SHORT faults are not checked.
1 = LED_OPEN and LED_SHORT faults are checked.
0x01 [2]
PH_SHIFT
R/W
0x01 [1]
INT_DUTY
R/W
Enables String-by-String phase shifting. This is a don’t care if INT_PWM=0.
0 = Phase shifting disabled.
1 = Phase shifting is enabled.
Determines the duty cycle source. This is a don’t care if INT_PWM = 0.
0 = LED duty cycle is set by the PWMI input.
1 = LED duty cycle is set by the 10-bit duty cycle control registers.
0x01 [0]
INT_PWM
R/W
Sets the LED PWM dimming source.
0 = LED PWM dimming driven directly from the PWMI input source (direct PWM dimming).
1 = LED PWM dimming driven from an internal oscillator (required for phase-shifted PWM
dimming); enables the PLL.
Analog Dimming Control Register
Bit Field Definition Read / Write Description
0x02 [4:0] IDAC [4:0]
R/W
5-bit analog dimming register — The LED current can adjusted in 32 steps from 0mA to max
value determined by RISET.
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