Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

SI5324C-C-GM View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
MFG CO.
'SI5324C-C-GM' PDF : 72 Pages View PDF
Si5324
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Phase Noise
fout = 622.08 MHz
Symbol
CKOPN
Test Condition
100 Hz Offset
1 kHz Offset
Min
Typ
Max
Unit
–90
dBc/Hz
–106
dBc/Hz
10 kHz Offset
–121
dBc/Hz
100 kHz Offset
–132
dBc/Hz
1 MHz Offset
–132
dBc/Hz
Subharmonic Noise
SPSUBH Phase Noise @ 100 kHz
–88
–76
dBc
Offset
Spurious Noise
SPSPUR
Max spur @ n x F3
–93
–70
dBc
(n 1, n x F3 < 100 MHz)
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT
setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency
Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding
the lock time of your frequency plan.
3. LOCKT = 3.3 ms
12
Rev. 1.1
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]