CHOICE OF COMPONENTS
Output Voltage
The SiP1759 regulated output is set at 2.5 V for ship-
ment. It can be adjusted from 2.5 V to 5.5 V via resistor
divider network from VOUT to GND. R1 and R2 should
be kept in the 50 kΩ to 100 kΩ range for low power
consumption, while maintaining adequate noise immu-
nity. The value R1 is calculated using the following for-
mula:
R1 = R2((VOUT/VFB)-1)
VFB is nominally 1.235 V.
Capacitor Selection
The value for the CIN and COUT capacitors is 10 µF and
the value of the CX capacitor is 0.33 µF.
Capacitor selection for CIN, COUT and CX will have an
impact on the voltage output ripple, output current and
overall physical size of the circuit.
PRINTED CIRCUIT BOARD
SiP1759DB
Vishay Siliconix
Ceramic capacitors are recommenced for their low
ESR, (≤ 20 mΩ), which will help keep the output volt-
age ripple at a minimum.
Output Voltage Ripple
The SiP1759 automatically decides whether to be in
step up mode or step down mode depending on the
VIN, VOUT and current load conditions, therefore the
voltage output ripple will vary. In step-up mode the
voltage output ripple is higher than step-down mode.
But unless VIN is significant larger than VOUT
(VIN ≥ VOUT + 1 V), in heavy load the IC will slip from
buck mode to boost mode as necessary to charge the
transfer capacitor and the ripple will increase. Reduc-
ing the CX capacitor value will cause an increase in the
swit-ching frequency and a reduction of the output rip-
ple.
Top Silk Screen
Top Layer
Document Number: 73784
S-61383–Rev. A, 31-Jul-06
Bottom Layer
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