SLS System Logic Semiconductor
SL20T0081
PIN DESCRIPTION
Power Supply Pins
Pin Name
I/O
Function
VDD
VSS
VCI
V0
V1
V2
V3
V4
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Positive Power Supply.
System Ground.
Voltage Booster input pin. The power supply for the voltage booster. VCI input voltage
is the reference of boosted output voltage (VOUT) of voltage booster.
LCD driver supply voltage pins.
When the internal LCD power supply circuit is enabled, these voltages are generated by it.
When the internal LCD power supply circuit is disabled, these voltages must be supplied
externally, and they should have the following relationship.
VSS < V4 < V3 < V2 < V1 < V0
LCD Power Supply Circuit Pins
Pin Name
I/O
Function
CAP1+
CAP1-
CAP2+
CAP2-
CAP3+
CAP4+
VOUT
VEXT
IREF
VR
IRE
O
Voltage booster pin. Connect a capacitor between this pin and the CAP1- pin
O
Voltage booster pin. Connect a capacitor between this pin and the CAP1+ pin
O
Voltage booster pin. Connect a capacitor between this pin and the CAP2- pin
O
Voltage booster pin. Connect a capacitor between this pin and the CAP2+ pin
O
Voltage booster pin. (refer the application example to connecting a capacitor)
O
Voltage booster pin. (refer the application example to connecting a capacitor)
O
Voltage booster pin. Connect a capacitor between this pin and VSS.
This is the external reference voltage input pin of the LCD power supply circuit.
I
This pin is valid only when internal reference voltage circuit is disabled (IREF=0).
Internal reference voltage circuit enable pin.
I
IREF = 0 : Internal reference voltage circuit is disabled. External reference voltage is
inputted via VEXT pin.
IREF = 1 : Internal reference voltage circuit is enabled.
External V0 voltage adjustment pin.
I
VR pin is valid only when the internal voltage regulator resistors are not used (IRE=0)
Internal voltage regulator resistor enable pin.
This pin selects the resistors for the V0 voltage level adjustment.
I
IRE = 1 : Use the internal resistors
IRE = 0 : Do not use the internal resistors. The V0 voltage level is controlled by the
external resisters that connected among V0 pin and VR pin and VSS.