SM5841HS View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
MFG CO.
'SM5841HS' PDF : 20 Pages View PDF
SM5841H
FUNCTIONAL DESCRIPTION
The basic arithmetic block is shown in figure 1, and
the function of each block is described in the follow-
ing sections.
Input
fs
Deemphasis IIR filter
fs
fs
Attenuator
fs
1st FIR
69th - order
2 × interpolator
2fs
2nd FIR
13th - order
2 × interpolator
4fs
3rd FIR
9th - order
2 × interpolator
8fs
Output
Figure 1. Arithmetic block diagram
8-times Oversampling (Interpolation)
Digital Deemphasis (DSF1, DSF2)
The interpolation arithmetic block is comprised of 3
cascaded, 2-times FIR interpolation filters, as shown
in figure 1.
The input signal is sampled at rate fs, and then 8-
times oversampling data is output. Sampling noise in
the 0.5465fs to 7.4535fs stopband is removed by the
interpolation filter.
The digital deemphasis filter has the same construc-
tion as analog filters. It is implemented as an IIR fil-
ter to faithfully reproduce the gain and phase
characteristics of standard analog deemphasis filters.
The filter coefficients for fs = 32.0/44.1/48.0 kHz
sampling frequency are selected by DSF1 and DSF2
when the sampling frequency is specified, as shown
in the following table.
DSF1
LOW
LOW
HIGH
HIGH
DSF2
LOW
HIGH
LOW
HIGH
Deemphasis Sampling frequency
On
44.1 kHz
On
48.0 kHz
Off
–
On
32.0 kHz
NIPPON PRECISION CIRCUITS—11
Share Link: 
