SM5846AP View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
MFG CO.
'SM5846AP' PDF : 36 Pages View PDF
SM5846AP
Internal control flag/D-ATT attenuator register initial values
Register
D-ATT attenuation
Mode flag 1
Mode flag 2
Mode flag 3
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
0
a1 = 0
a2 = 0
a3 = 0
a4 = 0
a5 = 0
a6 = 0
a7 = 0
1
0
SYNC = 1 TEST1 = 0 HS = 1 FSEL1 = 1 FSEL2 = 1 DEEM = 0
1
1
MUTE = 1 DITH = 1 OBS = 0 IBS1 = 1 IBS2 = 0
1
1
1
ASEL1 = 1 ASEL2 = 1
1
TEST2 = 1
1
0
When external muting is required
The SM5846AP has a relatively long group delay
time because multi-stage filters are employed to
achieve the desired filter characteristics. Under the
following conditions, undesirable noise output can
occur during the group delay time period. In this
case, it may be necessary to use external muting.
I When power is first applied.
The state of internal registers may be undefined
during power-ON.
I When switching the operating mode.
When switching the operating mode using HS,
ASEL1 and ASEL2, the internal register assign-
ments may be changed.
I If the LRCI and/or XTI clock stop.
If a disturbance occurs during an input data cycle,
normal filter output may not be achieved.
I When switching deemphasis ON/OFF.
Switching the deemphasis filter parameters may
cause switching noise output.
I When switching the sampling frequency (clock
frequency).
I When switching between input/output data for-
mats (including LRCI clock polarity switching).
Note that switching MDS is inhibited during system
operation.
Test Precautions
The following conditions should be maintained for
normal operation.
I MDS and DITH inputs should not be simulta-
neously LOW.
I TEST1 (bit 4 of mode flag 1 register) should not
be set to 1.
I TEST2 (bit 4 of mode flag 3 register) should be set
to 0 after system reset (including power-ON).
I Mode flag 3 register bit 5 and/or bit 7 should not
be set to 0.
SEIKO NPC CORPORATION —35
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