SM5876AM View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
MFG CO.
'SM5876AM' PDF : 17 Pages View PDF
SM5876AM
Infinity-Zero Detector (analog mute control) Output (MUTEO)
The SM5876AM outputs an infinity-zero detection
output signal under the following circumstances.
1. When an infinity-zero occurs on both the left and
right channels.
2. When an infinity-zero occurs in the input data for
the channel set by the output mode setting.
3. When the output mode setting is muting for both
the left and right channels.
4. When the attenuation counter for both the left and
right channels is 0 (−∞).
Also from immediately after a reset input on RSTN
until the initialization cycle finishes and the first data
cycle occurs.
In cases 1 and 2, from when an infinity-zero is
detected a period of 214 × (1/fs) ≈ 0.37 seconds takes
place before MUTEO goes HIGH.
In cases 3 and 4, from when the attenuation counter
value is 0 a period of 214 × (1/fs) ≈ 0.37 seconds
takes place before MUTEO goes HIGH.
LRCI
1
2
3
8
9
214/fs
DI
Signal
No Signal
Signal
RSTN
MUTEO
Initialize
Figure 2. MUTEO output timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first,
2s-complement, 16-bit serial format.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of
the bit clock BCKI.
The arithmetic operation and output timing are inde-
pendent of the input timing. Accordingly, after a
reset, as long as the clock frequency ratio between
LRCI and the system clock XTI is maintained, phase
differences between LRCI, BCKI and the system
clock XTI do not affect the functional operation.
Also, any jitter present on the data input clock does
not appear as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
Operating Modes (MLEN, MDT, MCK)
The microcontroller data is used to control the fol-
lowing parameters.
Digital attenuator
Digital attenuation is controlled by attenuation data
input on MDT.
The attenuation operation is determined by a mathe-
matical operation of the internal 8-bit up/down
counter’s output data on the signal data. The 8-bit
up/down counter, when attenuation data is input on
MDT, can control the left and right channels either
independently or together (independent when the
MDT attenuation control flag is LOW, and together
when HIGH).
The left-channel counter contents DATTL and the
right-channel counter contents DATTR control the
left-channel gain and right-channel gain, respec-
tively, using the following equations.
Left-channel
gain
=
20
×
log
D-----A-2---5T---5-T---L---
[dB]
Right-channel
gain
=
20
×
log
D-----A-2---5T---5-T---R---
[dB]
After system reset initialization, independent
left/right-channel attenuation mode with the maxi-
mum gain of 0 dB is the default.
Deemphasis filter (MDT DEM flag)
The built-in digital deemphasis filter is designed to
operate at 44.1 kHz. Deemphasis is ON when the
DEM flag is HIGH, and OFF when the DEM flag is
LOW. After reset, deemphasis OFF is the default.
NIPPON PRECISION CIRCUITS—14
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