SM5877AM View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
MFG CO.
'SM5877AM' PDF : 16 Pages View PDF
SM5877AM
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, DS)
The system clock on XTI can be set to run at one of Note that the input clock accuracy and signal-to-
two speeds, 384fs (normal speed) or 192fs (double- noise ratio greatly influence the AC analog character-
speed), where fs is the input frequency on LRCI. The istics. Accordingly, care should be taken to ensure
speed for CD playback is set by the input level on that the clock is free from jitter.
DS, as shown in table 1. The system clock should be
fixed at 16.9344 MHz.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
Table 1. System clock select
XTI and XTO and the built-in CMOS inverter. Alter-
natively, an external system clock can be input on
DS
XTI. As the internal CMOS inverter has a feedback
Parameter Symbol
LOW
(normal
speed)
HIGH
(double
speed)
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
XTI input clock
frequency
CD playback
XTI frequency
fXI
(= 1/tXI)
384fs
192fs
16.9344 MHz 16.9344 MHz
fXI
at fs = 44.1 at fs = 88.2
kHz
kHz
CKO output
clock frequency
fCO
384fs
192fs
Internal system
clock period
TSYS
tXI
tXI
System Reset (RSTN)
The device should be reset in the following cases.
s At power ON
s When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
RSTN
LRCI
LOW
1
2
3
9
10
Internal reset
LO
Outputs muted
RO
Figure 1. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-
complement, 16-bit serial format.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
The arithmetic operation and output timing are inde-
pendent of the input timing. Accordingly, after a reset,
as long as the clock frequency ratio between LRCI
and the system clock XTI is maintained, phase dif-
ferences between LRCI, BCKI and the system clock
XTI do not affect the functional operation. Also, any
jitter present on the data input clock does not appear
as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
NIPPON PRECISION CIRCUITS—13
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