SM5L1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'SM5L1' PDF : 27 Pages View PDF
4-Bit Single Chip Microcomputers
SM5L1/SM5L2/SM5L3
BOOSTER CIRCUIT
The device contains a booster circuit which gener-
ates a voltage two time higher than 1.5 V power supply.
It is necessary to apply external capacitors between
DDC pin and VCC pin as well as VDD pin and GND (see
Figure 30).
DDC
VCC
C1 = 0.1 µF (TYP.)
VDD
SM5Lx
C2 = 0.1 µF (TYP.)
Figure 30. Booster Circuit
5L1-30
BLANK DISPLAY
There are two ways blank the entire display to match
the purpose.
• Blanking the display for a short time
– Set bit 0 of the RF register to ‘1’: Display
– Set bit 0 of the RF register to ‘0’: Blank state
• Blanking the display for a long period mainly to
reduce supply current.
– Set bit 0 and 1 of the RF register to ‘1’: Display
– Set bit 0 and 1 of the RF register to ‘0’: Blank state
When bit 1 of the RF register is set ‘0’, the booster cir-
cuit does not operate and the common outputs and seg-
ment outputs are fixed to VM level, and the display
blanks. By cutting off the function of the booster circuit,
the supply current can be greatly reduced. However,
when the display is blanked using the second method,
the response speed of the LCD returning to the display
state drops slightly. The RF register is on the blank state
after initialization (reset state) from hardware reset.
INSTRUCTION SET
Definition of Symbols
The following symbols are used in descriptions for
the instructions.
SYMBOL
M
←
∪
∩
⊕
Ai
Push
Pop
Pj
Rj
ROM ( )
Cy
DEFINITION
Content of RAM at the address specified by
the B register
Transfer direction
Logical OR
Logical AND
Logical XOR
ith bit of the ACC
Contents of the PC are decremented to the
stack register
The decremented contents are transferred
back to the PC
Pj register (j = 3, 2, 1, 0)
Rj register (j = F, E, D)
ROM contents for address within ( )
Carry of ALU (different from the C flag)
• Each bit of a register can be represented. For exam-
ple the ith bit of X register and R(0) register are rep-
resented as Xi and R(0) i. (i = 0, 1, 2, 3, …)
• Increment and decrement denote the binary addition
of 1H and FH, respectively.
• To skip a certain instruction means that the instruc-
tion is ignored and that no operation is performed
until the execution transfers to the next instruction. In
other words, the instruction is regarded as a NOP
instruction. Therefore, one cycle is required to skip a
one-word instruction and two cycles are required to
skip a two word instruction.
ROM Address Control Instructions
MNE-
MONIC
TR x
TL xy
TRS x
CALL xy
RTN
RTNS
RTNI
MACHINE
CODE
80 to BF
E0 to EF
00 to FF
C0 to DF
F0 to FF
00 to FF
7D
7E
7F
OPERATIONS
PL ← x (I5 –I0)
PU ← x (I11 –I6)
PL ← y (I5 –I0)
Push, PU ← 01H,
PL ← x (I4, I3, I2, I1, I0, 0)
Push, PU ← x (I11 –I6)
PL ← y (I5 – I0)
Pop
Pop, skip the next step
Pop, IME ← 1
Microcomputer Data Sheet
23
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