SMC512BFY6 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
SMC512BFY6
Numonyx -> Micron
'SMC512BFY6' PDF : 91 Pages View PDF
SMCxxxBF
Electrical interface
Table 9. Signal Description (continued)
Signal Name
Dir.
Pin
–CD1, –CD2
(PC Card Memory Mode)
–CD1, –CD2
(PC Card I/O Mode)
–CD1, –CD2
(True IDE Mode)
O
26,25
–CE1, –CE2
(PC Card Memory Mode)
–CE1, –CE2
(PC Card I/O Mode)
I
7,32
–CS0, –CS1
(True IDE Mode)
–CSEL
(PC Card Memory Mode)
–CSEL
(PC Card I/O Mode)
I
39
–CSEL
(True IDE Mode)
–IOWR
(PC Card Memory Mode)
–IOWR
(PC Card I/O Mode)
I
35
–IOWR
(True IDE Mode)
–OE
(PC Card Memory Mode)
–OE
I
9
(PC Card I/O Mode)
–ATASEL
(True IDE Mode)
Description
These are connected to ground on the Card. They are used
by the host to determine that the Card is fully inserted into
its socket.
Same for all modes.
Same for all modes.
Used to select the Card and to indicate whether a Byte or a
Word operation is being performed. –CE2 accesses the odd
Byte, –CE1 accesses the even Byte or the odd Byte
depending on A0 and –CE2. A multiplexing scheme based
on A0, –CE1, –CE2 allows 8 bit hosts to access all data on
D0 to D7.
Same as PC Card Memory Mode.
–CS0 is the chip select for the task file registers, while –CS1
selects the Alternate Status Register and the Device
Control Register.
When –DMACK is asserted, -CS0 and –CS1 must be de-
asserted and data width is 16 bits.
Not used.
Not used.
This internally pulled up signal is used to configure the Card
as a Master or Slave. When grounded it is configured as a
Master, when open it is configured as a Slave.
Not used.
The I/O Write strobe pulse is used to clock I/O data on the
bus into the Card controller registers. Clocking occurs on
the rising edge.
Same as PC Card I/O Mode.
This is an Output Enable strobe generated by the host
interface. It reads data and the CIS and configuration
registers.
Reads the CIS and configuration registers.
This input signal must be driven Low to enable True IDE
mode.
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