SMC512BFY6 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
SMC512BFY6
Numonyx -> Micron
'SMC512BFY6' PDF : 91 Pages View PDF
SMCxxxBF
Card Configuration
Table 27. CompactFlash Memory Card Configurations
Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Mapping Mode
0
0
0
0
0
0
Memory
0
0
0
0
0
1 Contiguous I/O
0
0
0
0
1
0
Primary I/O
0
0
0
0
1
1 Secondary I/O
Card
Mode
Memory
I/O
I/O
I/O
Task File Register Address
0h - Fh, 400h - 7FFh
xx0h - xxFh
1F0h - 1F7h, 3F6h - 3F7h
170h - 177h, 376h - 377h
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Card Configuration and Status Register (202h in Attribute
Memory)
The Card Configuration and Status Register contains information about the Card’s status
(see Table 28).
Changed
Indicates that one or both of the Pin Replacement register (CRDY, or CWProt) bits are set to
‘1’. When the Changed bit is set, –STSCHG (Pin 46) is held Low and if the SigChg bit is ‘1’
the Card is configured for the I/O interface.
SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the
Status Register (issued on Status Changed pin 46). If no state change signal is desired, this
bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the Card is configured for
I/O.
IOis8
The host sets this bit to ‘1’ if the Card is to be configured in 8 bit I/O Mode. The Card is
always configured for both 8 and 16 bit I/O, so this bit is ignored.
PwrDwn
This bit indicates whether the Card is in the power saving mode or active mode. When the
PwrDwn bit is set to ‘1’, the Card enters power down mode. When set to ‘0’, the Card enters
active mode. The READY value on Pin Replacement Register becomes BUSY when this bit
is changed. READY will not become Ready until the power state requested has been
entered. The Card automatically powers down when it is idle and powers back up when it
receives a command.
Int
This bit represents the internal state of the interrupt request. It is available whether or not
the I/O interface has been configured. It remains valid until the condition which caused the
interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device
Control Register, this bit is ‘0’.
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